module Reg_EX_MEM (
    input wire clk,
    input wire rst,

    input wire [31:0] EX_ALU_C,
    input wire [31:0] EX_rd2,
    input wire [4:0] EX_RF_waddr,
    input wire [31:0] EX_pc,
    input wire [31:0] EX_pc4,
    input wire [31:0] EX_sext_ext,
    input wire EX_rf_we,
    input wire [1:0] EX_rf_wsel,
    input wire EX_ram_we,
    input wire [2:0] EX_Ld_op,
    input wire [2:0] EX_S_op,

    output reg [31:0] MEM_ALU_C,
    output reg [31:0] MEM_rd2,
    output reg [4:0] MEM_RF_waddr,
    output reg [31:0] MEM_pc,
    output reg [31:0] MEM_pc4,
    output reg [31:0] MEM_sext_ext,
    output reg MEM_rf_we,
    output reg [1:0] MEM_rf_wsel,
    output reg MEM_ram_we,
    output reg [2:0] MEM_Ld_op,
    output reg [2:0] MEM_S_op
);

always @(posedge clk or posedge rst) begin
    if(rst) MEM_ALU_C <= 0;
    else MEM_ALU_C <= EX_ALU_C; 
end


always @(posedge clk or posedge rst) begin
    if(rst) MEM_rd2 <= 0;
    else MEM_rd2 <= EX_rd2; 
end

always @(posedge clk or posedge rst) begin
    if(rst) MEM_RF_waddr <= 0;
    else MEM_RF_waddr <= EX_RF_waddr; 
end

always @(posedge clk or posedge rst) begin
    if(rst) MEM_pc <= 0;
    else MEM_pc <= EX_pc; 
end


always @(posedge clk or posedge rst) begin
    if(rst) MEM_pc4 <= 0;
    else MEM_pc4 <= EX_pc4; 
end

always @(posedge clk or posedge rst) begin
    if(rst) MEM_sext_ext<= 0;
    else MEM_sext_ext <= EX_sext_ext; 
end

always @(posedge clk or posedge rst) begin
    if(rst) MEM_rf_we <= 0;
    else MEM_rf_we <= EX_rf_we; 
end

always @(posedge clk or posedge rst) begin
    if(rst) MEM_rf_wsel <= 0;
    else MEM_rf_wsel <= EX_rf_wsel; 
end

always @(posedge clk or posedge rst) begin
    if(rst) MEM_ram_we <= 0;
    else MEM_ram_we <= EX_ram_we; 
end

always @(posedge clk or posedge rst) begin
    if(rst) MEM_Ld_op <= 0;
    else MEM_Ld_op<= EX_Ld_op; 
end

always @(posedge clk or posedge rst) begin
    if(rst) MEM_S_op <= 0;
    else MEM_S_op<= EX_S_op; 
end

    
endmodule